Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD's well below the available light source wavelengths. For instance the current production wavelength of 248 nm is being pushed towards patterning of CD's smaller than 100 nm. This industry trend will continue and possibly accelerate in the next 5–10 years, as described in the International Technology Roadmap for Semiconductors (ITRS 2000).
One technique, which is currently receiving additional attention from the photolithography community, for further improving the resolution/printing capabilities of photolithography equipment is referred to as chromeless phase lithography “CPL”. As is known, when utilizing CPL techniques, the resulting mask pattern typically includes structures (corresponding to features to be printed on the wafer) which do not require the use of chrome (i.e., the features are printed by phase-shift techniques) as well as those that utilize chrome. Such phase shift masks have been disclosed in U.S. Pat. Nos. 6,312,854 and 6,335,130, both of which are herein incorporated by reference.
It is necessary for mask designers to verify that the mask structures utilizing the various techniques all interact in an acceptable manner such that the desired pattern is printed on the wafer. Further, it is highly desirable that as the CDs of the features to be printed vary, the CDs are reproduced accurately. In other words, it is highly desirable that there is “linear” behavior when printing CDs of various widths (i.e., the CD linearity curve should be linear) in order to facilitate the manufacturing process, and minimize the need for multiple illuminations with different settings to obtain acceptable results.
Several solutions are currently known for achieving CD linearity. These solutions include CPL halftoning, and the use of scattering bars for OPC.
Scattering bars (SB) OPC often include changing “local transmission” by placing the SBs near the main feature edges. SBs can modulate the aerial image slope. FIGS. 1–3 illustrate the SB effect for aerial imaging modulation, the SB size effect, and the SB placement effect, using a generic DUV/ArF (193 nm)/4x and NA=0.75, quasar (0.87, 0.57). FIG. 1 illustrates a dose profile depicting the case of no SB, a 50 nm center SB and a 50 nm double SB. FIG. 2 illustrates a plot of CD vs. pitch for a 25 mJ-0.24 threshold chromeless mask (CLM) with chrome scattering bars (Cr SB) at 80 nm separation, for the cases of no SB (dots), a 20 nm SB (circles), a 30 nm SB (“+” signs), a 40 nm SB (“x”s), and a 50 nm SB (boxes). FIG. 2 indicates that a larger SB size causes a high feature CD. For example, in the case of a 20 nm SB, the main feature CD is 95 nm for a pitch of 550 nm (X-axis), and for the case of a 50 nm SB, the main feature CD is 125 nm for a pitch of 550 nm.
FIG. 3 illustrates another plot of CD vs. pitch for a 25 mJ-0.24 threshold CLM with Cr SB at various separations, for the cases of no SB (dots), a 70 nm separation (circles), an 80 nm SB separation (“+” signs), a 90 nm SB separation (“x”s), a 100 nm SB separation (boxes), a 110 nm SB separation (solid boxes), a 120 nm SB separation (triangles), a 130 nm SB separation (circle on white), a 140 nm SB separation (bars), a 150 nm SB separation (“x”s on black), and a 160 nm SB separation (boxes). FIG. 3 depicts the effect of SB placement (SB separation from the main feature edges), and that closer SB placement causes high feature CDs. For example, for a SB at 70 nm, the main feature CD is 110 nm for a pitch of 550 nm (X-axis), and for a SB at 160 nm, the main feature CD is ˜77 nm for a pitch of 550 nm.
While such solutions can be utilized in certain situations, in many circumstances, such solutions become exceedingly difficult to implement. For example, in certain mask designs, it can be exceedingly difficult to insert SBs having the desired dimensions in the necessary location.
Accordingly, there exists a need for a method and technique which provides a simple and systematic approach for defining and maintaining “linear” behavior with regard to the printing of CDs, as the CDs of the features contained in the given mask pattern vary.